As semiconductor devices scale to smaller dimensions, the ability to harness device improvements with decreased size becomes more challenging. The synthesis of three-dimensional semiconductor transistors, such as fin type field effect transistors (finFET), involves challenging processing issues. In many finFET designs, isolation of devices along a given fin is accomplished using trench isolation. To isolate a given portion of a fin for forming a transistor device, a pair of trench structures may be formed within the fin, by etching the fin to form trenches, and subsequently filling the trenches with an insulator, such as silicon oxide or other material. These trench structures may have a non-ideal shape, where the width of the trenches decreases with increasing depth from the surface of the trench. Such tapered trench structures may provide unsuitable device isolation. Moreover, proper filling of the trench structures with insulator may be difficult, especially for high-aspect ratio trenches where the ratio of trench depth/trench width exceeds 2-3.
With respect to these and other considerations, the present disclosure is provided.